In the fabrication of a semiconductor device, in particular, a memory, memory cells thereof are formed by use of a grid-like repetitive pattern in order to attain higher density of the memory cells. There is broadly described hereinafter a resist pattern for use in the steps of forming floating gates and control gates in the process of fabricating, for example, an EEPROM (Electrically Erasable Programmable ROM) with reference to FIGS. 9 through 11.
First, a gate oxide 211 and polysilicon film (not shown) are  formed in that order on the entire top surface of a substrate 201 with an isolation oxide film 210 formed thereon. Subsequently, a striped resist pattern having spacing portions 203 where a resist is removed and left-out portions 204 where the resist remains, as shown in FIG. 9, is transferred by photolithography to a memory cell section in its entirety in order to form end faces of the floating gates, in one direction, on the polysilicon film. In this case, a positive resist is used for the resist by way of example.
The polysilicon film is etched by using the striped resist pattern formed across the memory cell section as a mask. A width of respective portions of the polysilicon film, thus left out without being etched, determines a width of the respective floating gates, along the longitudinal direction thereof, corresponding to a direction in which respective control gates are extended. Thereafter, an insulating film 213, and an electrode polisilicon (not shown) serving as control gates 221 are sequentially formed across the surface of the memory cell section, and subsequently, a resist pattern shown in FIG. 10 is transferred thereto by photolithography. The electrode polisilicon is etched by use of left-out portions 206 of the resist pattern as masks, thereby forming the control gates 221.
Further, in order to form the floating gate 220 under the respective control gates 221, the polysilicon film is etched by use of the control gates 221 as masks, whereupon the floating gates 220 are formed. Thereafter, the formation of regions for a source 223 and drain 224, respectively, metallization, and so forth are performed, thereby completing each of the memory cells. FIG. 11A is a schematic plan view of the memory cell section after the fabrication of the memory cells, and FIG. 11B is a schematic sectional view of the memory cell, taken on line C—C in FIG. 11A.
Herein, write operation is described with reference to FIG. 11B. Assuming that a voltage applied to the control gate 221 is Vpp, capacitance between the floating gate 220 and an active layer 202 is Cu, capacitance between the floating gate 220 and the control gate 221 is Cd, and charge inside the floating gate 220 is Qf, a voltage Vfg of the floating gate 220 can be expressed by the following equation:Vfg={Vpp/(1+Cd/Cu)}+Qf/(Cd+Cu)Prior to the write operation, the second term of the equation is negligible as compared with the first term, and Cu is at a large value in comparison with Cd, so that Vfg becomes a voltage sufficient for inducing a channel, whereupon all memory cell transistors are turned into the “on” state.
At this point in time, if a predetermined voltage is applied between the drain 224 and source 223 of the memory cell where a program is executed, large current flows through the channel, and channel electrons having high energy are injected into the floating gate after passing over a barrier of the gate oxide, in the vicinity of the drain, whereupon the write operation is executed. As is evident from the equation for Vfg, the higher a Cu/Cd ratio is, the more write efficiency is enhanced. Accordingly, it will lead to enhancement in the write efficiency to enlarge an area of the floating gate, opposite to the control gate.
In FIG. 11A, the floating gate 220 is defined by a gate size 232 and a floating gate width 233. Since the gate size 232 is decided upon by a speed, and so forth, as set when designing a device, alteration thereof is not possible, however, since the floating gate width 233 is defined by the resist pattern for etching the polysilicon film, formed after depositing polysilicon across the top surface of the substrate, as previously described, it is conceivable to enlarge the floating gate width 233.
Nevertheless, a spacing between the floating gates 220 adjacent to each other has already been rendered minute in dimension, dependent on the resolving power of the photolithography, so that it is not possible to further narrow down the spacing. Accordingly, it has been difficult to expand the floating gate width 233, and consequently, it has been impossible to enlarge the area of the floating gate, opposite to the control gate.
Now, techniques for causing the resist to undergo deformation by use of thermal flow treatment to thereby form a resist pattern with dimensions less than the resolution limit of a pattern exposure system, or to control the deformation have been disclosed in a Patent Document as described below. With the use of the thermal flow treatment, it is possible to narrow down the spacing between the floating gates adjacent to each other. As with the case of the conventional techniques, after a polysilicon film is formed across the top surface of a substrate and a striped resist pattern is transferred to a memory cell section in its entirety, the thermal flow treatment is applied so as to cause thermal sagging, thereby causing dimensions of spacing portions of the resist pattern to be reduced. That is, a problem due to the resolution limit of the pattern exposure system can be overcome, thereby enabling the floating gate width 233 to be to enlarged
However, with a method of forming a minute resist pattern above the resolution limit of the pattern exposure system by use of the thermal flow treatment as described above, in the case of a resist pattern with stripes formed in a wide range covering the memory cell section in its entirety, since an amount of thermal sagging of the resist is insufficient and uneven, the amount of the thermal sagging of the resist for a memory cell 241 positioned in central parts of a memory cell section differs from that for a memory cell 242 positioned near the edges thereof, and a line of the resist pattern, along the shorter sides thereof, recedes as shown in FIG. 12, so that it has turned out that the method is unsuitable for the formation of the floating gates.
The invention has been developed to resolve the problems described above, encountered by the conventional method of fabricating a semiconductor device, and it is an object of the invention to provide a novel and improved method of fabricating a semiconductor device, capable of enlarging a gate width size of floating gates of a semiconductor memory device, and an area of the floating gate, opposite to the control gate, to thereby enhance write efficiency.